Word line drivers are configured to generate a word line signal carried by a word line which is received by memory cells of a memory array. The word line signal activates portions of the memory array to facilitate reading data from or programming data to the memory cells in the activated portions. In an existing approach, a logic level of the word line signal is determined using a first transistor and a second transistor. The first transistor is between the word line and an operating voltage. The second transistor is between the word line and a reference voltage. A gate of the first transistor is coupled to the operating voltage.
By coupling the gate of the first transistor to the operating voltage, the word line signal is susceptible to errors due to electrostatic discharge (ESD). During an ESD event, the operating voltage suddenly increases. In some instances, the first transistor allows the increased operating voltage to generate the word line signal. As a result, in some instances, the activated portions of the memory cell are erroneously programmed.
Erroneous programming is also a concern during a power on operation. In some instances, the word line driver receives a first operating voltage and a second operating voltage, where a voltage level of the first operating voltage is different than a voltage level of the second operating voltage. In instances where the first operating voltage is connected to the gate of the first transistor and fully powers on before the second operating voltage, the first transistor allows the first operating voltage to generate the word line signal. In such instances, the first operating voltage erroneously programs the activated portions of the memory array.